1. Field of Invention
The present invention relates to a method of manufacturing a dynamic random access memory (DRAM) capacitor. More particularly, the present invention relates to a method of manufacturing a DRAM capacitor that has tungsten upper and lower electrodes.
2. Description of Related Art
In this invention, a tungsten plug is used to connect with the source/drain region in a silicon substrate and form the upper and lower electrode of a capacitor. The lower tungsten electrode is formed using a chemical vapor deposition method, and hence the lower electrode has a roughened surface capable of increasing surface area. Furthermore, tantalum pentoxide, which has a relatively high dielectric constant, is used to form the dielectric layer, thus greatly increasing capacitance of the capacitor.
DRAM is a widely used integrated circuit component in the electronics industry. FIG. 1 is a circuit diagram showing one of the memory units of a DRAM device. As shown in FIG. 1, a memory unit is composed of a transfer transistor T and a storage capacitor C. The source terminal of the transfer transistor T is connected to a bit line BL, and the drain terminal is connected to the storage electrode 6 of the storage capacitor C. The gate terminal of the transfer transistor T is connected to a word line WL. On the other hand, the opposing electrode 8 of the storage capacitor C is connected to a fixed voltage source. Between the storage electrode 6 and the opposing electrode 8, there is a dielectric layer 7 separating the two. The capacitor C is a place for storing electronic data, and hence the capacitance of the capacitor must be sufficiently large to prevent loss of data.
For DRAMs having a memory capacity of less than 1 MB, two-dimensional capacitors known also as planar-type capacitors are generally sufficient to store the data. FIG. 2 is a schematic, cross-sectional diagram showing a planar-type capacitor within a memory unit. As shown in FIG. 2, the memory unit is formed by first providing a semiconductor substrate 10, and then forming field oxide layer 11 above the substrate 10. The field oxide layer 11 marks out the active region. Next, gate oxide layer 12, gate layer 13 and source/drain regions 14 are formed in sequence above the substrate 10, thereby creating a transfer transistor T. Thereafter, a dielectric layer 7 and a conductive layer 8 are formed in sequence over the substrate 10 adjacent to the drain terminal. The conductive layer 8, the dielectric layer 7 and a portion of the substrate surface 6 together form a storage capacitor C. As is obvious from FIG. 2, a planar-type capacitor must occupy a large substrate area so that sufficient capacitance can be provided. Hence, this type of capacitor is unsuitable for the production of highly integrated DRAM devices.
In general, for highly integrated DRAM with storage capacity greater than 4 MB, a three-dimensional capacitor structure must be used. Three-dimensional capacitor structures fall into two main categories, namely, the stack-type and the trench-type.
FIG. 3 is a schematic, cross-sectional view of a conventional stack-type capacitor in a memory unit. As shown in FIG. 3, the stack-type capacitor is formed by first providing a semiconductor substrate 10. Then, a transfer transistor T is constructed over the substrate 10 by forming field oxide layer 11, gate oxide layer 12, gate layer 13 and source/drain regions 14 in turn. Next, an insulating layer 15 is formed over the substrate structure, and then the insulating layer 15 is etched to form a contact opening above the source/drain region 14.
Thereafter, a second polysilicon layer 6 (serving as a storage electrode), a dielectric layer 7 and a conductive layer 8 (serving as an opposing electrode) are sequentially formed in layers above the contact opening. Hence, a capacitor C having a three-dimensional structure is formed. The capacitor C is capable of providing a sufficiently large amount of capacitance within a small area. However, as the level of integration continues to increase, construction of a DRAM with a capacity of more than 64 MB, for example, using the simple, stack-type of capacitor structure is unable to meet memory demands.
FIG. 4 is a schematic, cross-sectional view of a conventional trench-type capacitor in a memory unit. The method of forming a trench-type capacitor includes the steps of first forming a transfer transistor T over a semiconductor substrate 10. The transfer transistor T comprises a gate oxide layer 12, a gate layer 13 and source/drain regions 14. Thereafter, a deep trench is etched out in the substrate 10 in the neighborhood of the drain region 14. In the subsequent step, a storage capacitor C is formed inside the trench. The capacitor C includes a storage electrode 6 made from the substrate material forming the sidewalls and bottom of the trench, a dielectric layer 7 and an opposing electrode 8 made from a layer of polysilicon. Although the trenchtype capacitor is able to increase surface area of the electrode and hence its capacitance, the process of etching the substrate to form a trench may be accompanied by formation of a large number of crystal defects.
Consequently, leakage current within the substrate may be produced. Furthermore, as aspect ratio of the trench continues to increase due to miniaturization, etching rate will correspondingly decrease. Hence, processing operations are more difficult to carry out and production efficiency drops.
FIG. 5 is a schematic, cross-sectional view of a conventional DRAM capacitor having a polysilicon/HSG/ONO multiple-layered structure. In FIG. 5, a polysilicon layer 340 and a hemispherical silicon grain (HSG) layer 400 are formed to act as the lower electrode so that surface area is increased. Moreover, an oxide/nitride/oxide (ONO) triple-layered structure 500 is formed to serve as the dielectric layer of the capacitor. However, when the design rules for forming 0.25 .mu.m devices are applied, the capacitor is still incapable of reaching a capacitance of 25 fF.
Therefore, problems facing conventional DRAM capacitors include:
1. A planar-type of capacitor has to occupy a large surface area in order to provide sufficient capacitance. Hence, it is unsuitable for forming highly integrated DRAM devices.
2. For DRAM having a capacity greater than 4 MB, three-dimensional-type of capacitor such as the stack-type or the trench-type of capacitor must be used. However, as memory capacity continues to increase to about 64 MB or more, even the stack-type of capacitor is unable to provide sufficient capacitance.
3. Although the conventional, trench-type capacitor is able to increase surface area and increase capacitance, the process of etching the substrate to form a trench will generate greater number of crystal defects that can produce leakage current. Furthermore, as device continues to miniaturize, etching will be more difficult and the etching rate will be slower. Therefore, productivity will drop.
4. Although capacitance can increase somewhat if polysilicon, HSG and ONO triple-layered dielectric layer are added to a conventional capacitor, the design rules for a device with dimensions smaller than 0.25 .mu.m makes a capacitance of 25 fF difficult to attain.
In light of the foregoing, there is a need to provide an improved method of forming DRAM capacitor.